1. Field of the Invention
The present invention relates generally to a test structure and method for using the test structure during a semiconductor device manufacturing process. More particularly, the present invention relates to a test structure and related method for testing for metal failure in a semiconductor device. A claim of priority is made to Korean Patent Application No. 2003-42793, filed on Jun. 27, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety.
2. Description of the Related Art
Multilevel metalization processes are used to form multi-layered metal patterns during the manufacture of a semiconductor device. Metal patterns are typically formed on a semiconductor substrate as well as the intermediate layers and components forming the semiconductor device. Indeed, metal patterns, as formed in the respective layers constituting a semiconductor device, are essential to the operation of the device. Thus, a metal failure, when occurring, is particularly troublesome. A metal failure occurs, for example, if a metal pattern is formed on a semiconductor substrate with an electrically shorted or open connection. Any number of problems in the complex manufacturing process required to produce a contemporary semiconductor device may be the cause of a metal failure. Nonetheless, manufacturing yield dramatically falls as the number of metal failures increases.
Conventionally, optical test (or inspection) equipment is used to check for manufacturing defects such as metal failures. Although such optical test equipment effectively detects manufacturing defects, it is incapable of distinguishing (or classifying) a particular defect amongst a broad range of possible defects. In particular, important defects directly resulting in a serious decline in manufacturing yield are not specifically identified by the conventional test equipment. Furthermore, the process of optically scanning for defects using conventional test equipment requires considerable time. Accordingly, it is generally impractical to inspect every portion of every semiconductor wafer during manufacture. Yet, if only selected portions of each semiconductor wafer, or portions of a selected batch sample are checked, many defects will go undetected and unsatisfactory yield will occur.